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INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT (IJNRD)
An International Open Access Journal |   ISSN: 2456-4184 |  IMPACT FACTOR: 5.57

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Issue: June 2018

Volume 3 | Issue 6

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Paper Title: Design of Ring Oscillator based DDFS algorithm & architecture based on 0.18uM CMOS
Authors Name: Mainak Ghosh , Dr. Mrinal Kanti Mandal
Author Reg. ID:
IJNRD_170082
Published Paper Id: IJNRD1706018
Published In: Volume 2 Issue 6, June-2017
Abstract: This paper introduces a ring oscillator based novel DDFS technique for generation of fixed period synthesized output signal. Generally it is seen that DDFS designed using arithmetic circuits (Direct Analog) and loop based technique’s (PLL/VCO) provides synthesized signals with instantaneously varying time periods from a fixed period input clock signal. This type of synthesized signals create a major bottleneck when used in sensitive & precise application due to its time varying nature which in turn puts tight constraints on reference clock, power supply and system noise. In the presented work a RO based complete digital block ASIC architecture has been designed in which properly modulated input clock signal from RO is utilized to obtain a fixed period synthesized output signal. Presented synthesizer can be suitably incorporated for design of low power & area constrained VLSI architectures or programmable low scale integration processes with incorporated wide bandwidth range & low power consumption . Simulation result justify the proposed algorithm’s validity and its improvement in performance over arithmetic and loop based architecture’s
Keywords: ASIC, CMOS, Direct Digital Frequency Synthesis (DDFS), Frequency Synthesis, Ring Oscillator (RO)
Cite Article: "Design of Ring Oscillator based DDFS algorithm & architecture based on 0.18uM CMOS", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.2, Issue 6, page no.98-103, June-2017, Available :http://www.ijnrd.org/papers/IJNRD1706018.pdf
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