UGC approved journal IJNRD Research Journal


INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT (IJNRD)
An International Open Access Journal |   ISSN: 2456-4184 |  IMPACT FACTOR: 5.57

Call For Paper

Issue: August 2019

Volume 4 | Issue 8

Impact Factor: 5.57

Submit Paper Online

Click Here For more Details

For Authors

Forms / Download

Editorial Board

Subscribe IJNRD

Facts & Figure

Impact Factor : 5.57

Issue per Year : 12

Volume Published : 4

Issue Published : 39

Article Submitted : 576

Article Published : 357

Total Authors : 930

Total Reviewer : 541

Total Pages : 79

Total Countries : 21

Visitor Counter


Indexing Partner

Published Paper Details
Paper Title: Design and Implementation of Parallel Self-Timed Adder Using VHDL
Authors Name: Dr. Ahmed Sajjad Khan , Mohammad Hassan , Syed Aiman , Shreya Raut , Shefali Gedam
Author Reg. ID:
IJNRD_180036
Published Paper Id: IJNRD1804007
Published In: Volume 3 Issue 4, April-2018
Abstract: As technology scales down into the lower nanometer values power, delay, area and frequency becomes important parameters for the analysis and design of any circuits. This brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multi-bit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fan-outs. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders.
Keywords: CMOS design, digital arithmetic Binary adders, Recursive adder.
Cite Article: "Design and Implementation of Parallel Self-Timed Adder Using VHDL ", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.3, Issue 4, page no.45-49, April-2018, Available :http://www.ijnrd.org/papers/IJNRD1804007.pdf
Downloads: 000398
Share Article:

Click Here to Download This Article

Article Preview

ISSN Details

DOI (A digital object identifier)



Providing A digital object identifier by DOI

RMS

Conference Proposal

Latest News / Updates

Open Access License Policy

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License

Creative Commons License This material is Open Knowledge This material is Open Data This material is Open Content

Important Details

Social Media

IJNRD