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INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016 Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.76 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI) |
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| Paper Title: | DESIGN OF LOW-POWER SHIFT REGISTER USING GDI TECHNIQUE |
| Authors Name: | K.Kalaichelvi , C.Nivashini |
| Download E-Certificate: | Download |
| Author Reg. ID: |
IJNRD_216446
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| Published Paper Id: | IJNRD2403482 |
| Published In: | Volume 9 Issue 3, March-2024 |
| DOI: | |
| Abstract: | For the purpose of testing large-scale GDI circuits with delay-line clocking, propose and demonstrate a shift register. An essential circuit block in cryogenic studies is a pair of serializes, or parallel-to-serial converters, and deserializers, or serial-to-parallel converters. For example, apparatus like a cryostat and cry probe restrict the amount of available input/output (I/O) cables. Therefore, it is essential to minimize the number of I/O cables using a Sir/Des, particularly when testing a large-scale superconductor circuit. Shift registers, which hold data during serial-to-parallel (S2P) and parallel-to-serial (P2S) conversion, are used in RSFQ logic as serializes and deserializers. Regarding GDI logic, we have already suggested and illustrated the feedback-type SR, in which a shift register-like GDI buffer chain with feedback paths functions. However, because feedback routes in delay-line clocking are challenging to create due to the low latency, this Ser/Des was designed for four-phase clocking and does not function in that mode. As a result, we create the GDI hybrid SR, a unique SR for testing delay-line-clocked GDI circuits that combines GDI and RSFQ technology. |
| Keywords: | Large-scale GDI circuits, Cryogenic, RSFQ logic, GDI buffer chain. |
| Cite Article: | " DESIGN OF LOW-POWER SHIFT REGISTER USING GDI TECHNIQUE ", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.9, Issue 3, page no.e657-e669, March-2024, Available :http://www.ijnrd.org/papers/IJNRD2403482.pdf |
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2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID:IJNRD2403482 Registration ID: 216446 Published In: Volume 9 Issue 3, March-2024 DOI (Digital Object Identifier): Page No: e657-e669 Country: Karur, Tamilnadu, India Research Area: Electronics & Communication Engg. Publisher : IJ Publication Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD2403482 Published Paper PDF: https://www.ijnrd.org/papers/IJNRD2403482 |
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ISSN: 2456-4184
Impact Factor: 8.76 and ISSN APPROVED
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