Circuit and Layout Level Optimization of Logic Locking Circuits to Reduce Area

Registration ID: IJNRD_326065

Published ID: IJNRD2606354

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Mahesh G Shet, Dr. Meghana Kulkarni,, Tejswini Gull

Threats like intellectual property (IP) piracy reverse engineering overproduction and malicious modifications have made hardware security a significant challenge with the fast development of semiconductor technology and the globalization of the IC supply chain. By requiring a secret key to enable proper functionality logic locking has become an effective countermeasure that safeguards digital circuits. In order to lower hardware overhead and improve security this project offers an proposed transistor-level and gate level implementation of a logic-locked C17 benchmark circuit. The XOR gate is implemented using CMOS logic and six NAND gates are implemented using transmission-gate logic in the traditional logic-locked C17 benchmark design. A CMOS XOR gate needs twelve transistors whereas a transmission-gate NAND gate needs eight. This implementation increases the total number of transistors the layout area and the cost of fabrication even though it offers the necessary logic functionality and security. The six NAND gates are implemented using CMOS logic and the XOR gate is realized using transmission-gate logic in a novel design approach that addresses these shortcomings. Eight transistors are needed for the transmission-gate XOR gate compared to just four for the CMOS NAND gate. The suggested design drastically lowers the overall number of transistors by using a transmission-gate-based XOR gate and substituting CMOS NAND gates for the transmission-gate NAND gates. Compared to the conventional implementation this reduction directly results in a smaller layout area better area efficiency and less hardware overhead. As a transistor-level camouflaging method the suggested design uses dummy transistors in Layout. These dummy devices are positioned strategically to hide the true layout structure from attackers. This method of camouflaging makes reverse engineering more challenging and fortifies the logic-locked circuits defence against hardware intrusions. The suggested logic-locked C17 benchmark illustrates a successful trade-off between design efficiency and security. The design achieves enhanced hardware security with reduced implementation overhead by lowering the number of transistors and layout area while integrating camouflaging techniques making it a viable option for resource-efficient and secure VLSI applications.

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Mahesh G Shet, Dr. Meghana Kulkarni,, & Tejswini Gull (June-2026). Circuit and Layout Level Optimization of Logic Locking Circuits to Reduce Area. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 11(6), d515-d533. https://ijnrd.org/papers/IJNRD2606354.pdf

Volume 11 Issue 6, June-2026

Pages : d515-d533

Paper Reg. ID: IJNRD_326065

Published Paper Id: IJNRD2606354

Research Area: Other area not in list

Author Type: Indian Author

Country: Belagavi, Karnataka, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2606354.pdf

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