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INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016 Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.76 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI) |
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| Paper Title: | Design & Implementation of Self Time Dummy Replica Technique in 128x128 Low Voltage SRAM |
| Authors Name: | Mitali Agarwal , Taru Tevtia |
| Download E-Certificate: | Download |
| Author Reg. ID: |
IJNRD_160086
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| Published Paper Id: | IJNRD1704029 |
| Published In: | Volume 2 Issue 4, April-2017 |
| DOI: | |
| Abstract: | SRAM are useful building blocks in many applications such as cache memories, data storage embedded applications, microprocessors. The paper aims to propose the design for 128x128 SRAM with self time dummy replica technique for fast read & write access and low power consumption. The main functional blocks are 6T SRAM cell, row and column decoders, precharge circuit, read/write block and sense amplifier. Access time, speed & power consumption are the three key parameters for an SRAM memory design. Self time technique have been implemented to optimize power and access speed of SRAM. Memory timing circuits need a delay element which tracks the bit-line delay but still provide a large swing signal which can be used by the subsequent stages of the control logic. The key to building such a delay stage is to use a delay element which is a replica of the memory cell connected to the bit-line, while still providing a full swing output. This technique uses a dummy column and dummy row in the RAM to control the flow of signals through the core. The 128x128 SRAM has been designed, implemented & analyzed in standard TSMC 180nm technology library using Cadence Virtuoso tool. |
| Keywords: | SRAM, Decoder, Precharge Circuit, Sense Amplifier, Dummy column |
| Cite Article: | "Design & Implementation of Self Time Dummy Replica Technique in 128x128 Low Voltage SRAM ", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.2, Issue 4, page no.110-115, April-2017, Available :http://www.ijnrd.org/papers/IJNRD1704029.pdf |
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| ISSN: |
2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID:IJNRD1704029 Registration ID: 160086 Published In: Volume 2 Issue 4, April-2017 DOI (Digital Object Identifier): Page No: 110-115 Country: Aligarh, Uttar Pradesh, India Research Area: Engineering Publisher : IJ Publication Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD1704029 Published Paper PDF: https://www.ijnrd.org/papers/IJNRD1704029 |
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ISSN: 2456-4184
Impact Factor: 8.76 and ISSN APPROVED
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