|
|||||||||||||||
|
INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016 Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.76 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI) |
||||||||||||||
Issue: May 2024
Volume 9 | Issue 5
Review Result and Publication of Paper within : 2-3 days
Click Here For more DetailsFor Authors
Forms / Download
Published Issue Details
Editorial Board
Other IMP Links
Facts & Figure
Impact Factor : 8.76
Issue per Year : 12
Volume Published : 9
Issue Published : 96
Article Submitted :
Article Published :
Total Authors :
Total Reviewer :
Total Countries :
Indexing Partner
Join RMS/Earn 300
Licence
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
|
Published Paper Details
|
|
| Paper Title: | Low Power Transistor Stacking System in VLSI Circuits in 18nm |
| Authors Name: | MADDAL CHARYULU , MOVVA SAILAXMI |
| Download E-Certificate: | Download |
| Author Reg. ID: |
IJNRD_201989
|
| Published Paper Id: | IJNRD2307260 |
| Published In: | Volume 8 Issue 7, July-2023 |
| DOI: | |
| Abstract: | : Now a days, It is difficult to design a CMOS circuit without leakage current. One of the main difficulties in CMOS VLSI design is leakage power dissipation. Switching and short circuit leakage power have a big impact on how inputs transition dynamically at high frequencies. The power consumption of circuits can be reduced using a variety of widely accepted ways. There are some efficient ways to lower CMOS VLSI circuits' power dissipation. The power consumption of circuits can be reduced using a variety of common ways.We introduced a novel technology called LPTSS(Low power transistors stacking system) to mitigate circuit power reduction. CMOS logic devices' leakage power should be reduced, in this work designed a new stacking mechanism. To demonstrate how the suggested technique works in several CMOS logic circuits, including NAND, Inverter, NOR, and MUX, we used these circuits. To demonstrate the relative decrease in both time and power loss, as well as simultaneously compared the different reduction techniques with our suggested system. With the proposed system, inaccordance with reference to the traditional approaches such as Stack ONFIC, SAPON,etc. The Cadence tool uses 18nm technology to replicate all of the techniques listed. |
| Keywords: | LPTSSS,NAND,NOR,MUX,LCNT,LECTOR,SAPON,STACK ONOFIC |
| Cite Article: | "Low Power Transistor Stacking System in VLSI Circuits in 18nm ", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.8, Issue 7, page no.c621-c632, July-2023, Available :http://www.ijnrd.org/papers/IJNRD2307260.pdf |
| Downloads: | 000118762 |
| ISSN: |
2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
| Publication Details: |
Published Paper ID:IJNRD2307260 Registration ID: 201989 Published In: Volume 8 Issue 7, July-2023 DOI (Digital Object Identifier): Page No: c621-c632 Country: Hyderabad, Telangana, India Research Area: Electronics & Communication Engg. Publisher : IJ Publication Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD2307260 Published Paper PDF: https://www.ijnrd.org/papers/IJNRD2307260 |
| Share Article: |
|
|
Click Here to Download This Article |
|
| Article Preview | |
|
|
|
Major Indexing from www.ijnrd.org
| Semantic Scholar | Microsaoft Academic | ORCID | Zenodo |
| Google Scholar | ResearcherID Thomson Reuters | Mendeley : reference manager | Academia.edu |
| arXiv.org : cornell university library | Research Gate | CiteSeerX | PUBLON |
| DRJI | SSRN | Scribd | DocStoc |
ISSN Details
 |
 |
|
ISSN: 2456-4184
Impact Factor: 8.76 and ISSN APPROVED
Journal Starting Year (ESTD) : 2016
DOI (A digital object identifier)
Conference
Open Access License Policy
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
Important Details
Social Media
Licence
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
Join RMS/Earn 300
| Copyright © 2024 - All Rights Reserved - IJNRD |
Facebook Twitter Instagram LinkedIn