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INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT (IJNRD)
An International Open Access Journal |   ISSN: 2456-4184 |  IMPACT FACTOR: 5.57

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Volume 4 | Issue 7

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Paper Title: Design & Implementation of Self Time Dummy Replica Technique in 128x128 Low Voltage SRAM
Authors Name: Mitali Agarwal , Taru Tevtia
Author Reg. ID:
IJNRD_160086
Published Paper Id: IJNRD1704029
Published In: Volume 2 Issue 4, April-2017
Abstract: SRAM are useful building blocks in many applications such as cache memories, data storage embedded applications, microprocessors. The paper aims to propose the design for 128x128 SRAM with self time dummy replica technique for fast read & write access and low power consumption. The main functional blocks are 6T SRAM cell, row and column decoders, precharge circuit, read/write block and sense amplifier. Access time, speed & power consumption are the three key parameters for an SRAM memory design. Self time technique have been implemented to optimize power and access speed of SRAM. Memory timing circuits need a delay element which tracks the bit-line delay but still provide a large swing signal which can be used by the subsequent stages of the control logic. The key to building such a delay stage is to use a delay element which is a replica of the memory cell connected to the bit-line, while still providing a full swing output. This technique uses a dummy column and dummy row in the RAM to control the flow of signals through the core. The 128x128 SRAM has been designed, implemented & analyzed in standard TSMC 180nm technology library using Cadence Virtuoso tool.
Keywords: SRAM, Decoder, Precharge Circuit, Sense Amplifier, Dummy column
Cite Article: "Design & Implementation of Self Time Dummy Replica Technique in 128x128 Low Voltage SRAM ", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.2, Issue 4, page no.110-115, April-2017, Available :http://www.ijnrd.org/papers/IJNRD1704029.pdf
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