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IJNRD
INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016
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Impact Factor : 8.76

Issue per Year : 12

Volume Published : 9

Issue Published : 96

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Paper Title: Analysis of Domino logic based full adder
Authors Name: L. Vikas , T. Rajesh Reddy , P. Jeevan
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IJNRD_217645
Published Paper Id: IJNRD2404257
Published In: Volume 9 Issue 4, April-2024
DOI:
Abstract: Designing a circuit with low power, high speed performance is one of the challenging aspects. Since most recent VLSI devices are becoming portable, area-efficient devices are the most commonly utilized type. As the number of transistors will increase, correspondingly area, delay and power consumption of the device will also increase. Therefore, a technology is required by which the area can be reduced and increase the performance of the device. A fundamental component of multiplexer and processor designs is the full adder. It is possible to implement full adders with CMOS technology. A major factor influencing the CPU performance on VLSI circuit chips is the CMOS technology. In this project, implemented various full adder circuits using CMOS technology such as Standard Full adder circuit, Low Power Hybrid Full Adder, Full Adder Circuit using Modernized Full Sway Ex-or, Ex-nor gates and Domino logic based Full adder circuit. The analysis includes examining key parameters such as propagation delay, power consumption, and signal integrity. Findings from this analysis contribute to the enhancement of full adder designs, offering insights into potential optimizations and trade-offs. This project explores the design and performance analysis of a full adder circuit using Mentor Graphics tools.
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Cite Article: "Analysis of Domino logic based full adder ", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.9, Issue 4, page no.c249-c254, April-2024, Available :http://www.ijnrd.org/papers/IJNRD2404257.pdf
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ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID:IJNRD2404257
Registration ID: 217645
Published In: Volume 9 Issue 4, April-2024
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Page No: c249-c254
Country: Srikakulam , Andhra Pradesh , India
Research Area: Electronics & Communication Engg. 
Publisher : IJ Publication
Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD2404257
Published Paper PDF: https://www.ijnrd.org/papers/IJNRD2404257
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ISSN: 2456-4184
Impact Factor: 8.76 and ISSN APPROVED
Journal Starting Year (ESTD) : 2016

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